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Topaz 🐇<p>OK this is pretty cool. A project called DigitalJS can give you a visual layout of all of the logic that'll go into a Verilog design, using Yosys to do the generation. Being able to see what's being ultimately produced helps me, a much more visual person, understand when I've flubbed something that generates too much logic. I already optimized one piece of the display RAM using it. It's at <a href="https://digitaljs.tilk.eu/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="">digitaljs.tilk.eu/</span><span class="invisible"></span></a> but you can also run it locally. <a href="https://oldbytes.space/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://oldbytes.space/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://oldbytes.space/tags/ulx3s" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ulx3s</span></a></p>
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#verilog
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bleeptrack<p>If you wanna see me struggle with <a href="https://vis.social/tags/shaders" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>shaders</span></a> and <a href="https://vis.social/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> at the same time: I have a stream for you this evening!</p><p><a href="https://www.youtube.com/live/HSV3xF_TSqg?si=YmyPzEyXG5p8ryU1" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://www.</span><span class="ellipsis">youtube.com/live/HSV3xF_TSqg?s</span><span class="invisible">i=YmyPzEyXG5p8ryU1</span></a></p>
IT News<p>The Spade Hardware Description Language - Spade is an open-source hardware description language (HDL) developed at Linköping... - <a href="https://hackaday.com/2025/04/13/the-spade-hardware-description-language/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">hackaday.com/2025/04/13/the-sp</span><span class="invisible">ade-hardware-description-language/</span></a> <a href="https://schleuss.online/tags/hardwaredescriptionlanguage" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>hardwaredescriptionlanguage</span></a> <a href="https://schleuss.online/tags/spadelanguage" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>spadelanguage</span></a> <a href="https://schleuss.online/tags/hardware" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>hardware</span></a> <a href="https://schleuss.online/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://schleuss.online/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://schleuss.online/tags/asic" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>asic</span></a> <a href="https://schleuss.online/tags/vhdl" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>vhdl</span></a> <a href="https://schleuss.online/tags/hdl" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>hdl</span></a></p>
Jack<p>Hey all! I'm due for an (re-)introduction: I'm Jack, an engineer in the NYC area from a firmware & cybersecurity background, currently working in something like hardware-software co-design.</p><p>Technical work is often with <a href="https://recurse.social/tags/rust" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>rust</span></a> <a href="https://recurse.social/tags/kicad" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>kicad</span></a> <a href="https://recurse.social/tags/python" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>python</span></a> <a href="https://recurse.social/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://recurse.social/tags/c" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>c</span></a>, and in all-too-rare moments stuff like <a href="https://recurse.social/tags/haskell" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>haskell</span></a> <a href="https://recurse.social/tags/forth" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>forth</span></a> <a href="https://recurse.social/tags/agda" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>agda</span></a> and <a href="https://recurse.social/tags/prolog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>prolog</span></a><br> <br>I've never been much for social media, usually preferring to keep interests local: a better-detailed <a href="https://recurse.social/tags/introduction" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>introduction</span></a> to follow as I figure this out 🙂</p>
Flux<p>Is 2025 the year of <a href="https://mastodon.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a> on the desktop? 🤔 </p><p>Please suggest interesting FPGA projects and people to inspire us for the year ahead. 🚀</p><p>I'm working on a 2D graphics accelerator in <a href="https://mastodon.social/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> and <a href="https://mastodon.social/tags/riscv" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>riscv</span></a> assembler.</p>
IT News<p>Did You Know YoSys Knows VHDL Too? - We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while... - <a href="https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">hackaday.com/2024/12/04/did-yo</span><span class="invisible">u-know-yosys-knows-vhdl-too/</span></a> <a href="https://schleuss.online/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://schleuss.online/tags/yosys" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>yosys</span></a> <a href="https://schleuss.online/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://schleuss.online/tags/vhdl" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>vhdl</span></a></p>
Alfred M. Szmidt<p>Calling all <a href="https://mastodon.social/tags/HDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>HDL</span></a> hackers! I need help in putting the <a href="https://mastodon.social/tags/MIT" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>MIT</span></a> <a href="https://mastodon.social/tags/CADR" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>CADR</span></a> onto a FPGA board. <a href="https://mastodon.social/tags/VHDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>VHDL</span></a>, <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a>, does not matter much. Who is up for a fun challange? <a href="https://mastodon.social/tags/LispMachine" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>LispMachine</span></a></p>
Flux<p>The <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a> source for all four dev boards and Verilator simulation is available on GitHub under the MIT licence: <a href="https://github.com/projf/projf-explore/tree/main/graphics/fpga-graphics" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">github.com/projf/projf-explore</span><span class="invisible">/tree/main/graphics/fpga-graphics</span></a></p>
Flux<p><a href="https://mastodon.social/tags/ULX3S" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ULX3S</span></a> users are in a similar situation. You need the USRMCLK macro to access the SPI clock. Accessing the SPI clock on different dev boards is more time-consuming than writing the <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a> SPI module. 😅</p>
Flux<p>Now this looks like an interesting project: <a href="https://github.com/amaranth-lang/rtl-debugger" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">github.com/amaranth-lang/rtl-d</span><span class="invisible">ebugger</span></a></p><p>"VS Code based debugger for hardware designs in <a href="https://mastodon.social/tags/Amaranth" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Amaranth</span></a> or <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a>" </p><p>Can you tell us any more <span class="h-card" translate="no"><a href="https://mastodon.social/@whitequark" class="u-url mention" rel="nofollow noopener" target="_blank">@<span>whitequark</span></a></span> ?</p>
Flux<p>I have updated my guide to <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a> Simulation with Verilator and SDL to cover Windows as well as Linux and macOS.</p><p>If your Verilog project uses graphics, I can't recommend Verilator/SDL simulation highly enough. The turnaround time is *so* fast! <a href="https://mastodon.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a> ⏩ <a href="https://projectf.io/posts/verilog-sim-verilator-sdl/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">projectf.io/posts/verilog-sim-</span><span class="invisible">verilator-sdl/</span></a></p>
Amini Allight<p>Is it possible to multiply a clock in a Verilog testbench? It absolutely does not need to be synthesizable, this is purely for simulation<br>I can generate clocks of different frequencies with "always begin" + delays but I want to guarantee an edge alignment or a phase shift</p><p>Boosts for visibility appreciated!<br><a href="https://mastodon.gamedev.place/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://mastodon.gamedev.place/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://mastodon.gamedev.place/tags/hardware" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>hardware</span></a> <a href="https://mastodon.gamedev.place/tags/openhardware" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>openhardware</span></a></p>
IT News<p>Tiny Tapeout 4: A PWM clone of Covox Speech Thing - Tiny Tapout is an interesting project, leveraging the power of cloud computing and... - <a href="https://hackaday.com/2024/06/21/tiny-tapeout-4-a-pwm-clone-of-covox-speech-thing/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">hackaday.com/2024/06/21/tiny-t</span><span class="invisible">apeout-4-a-pwm-clone-of-covox-speech-thing/</span></a> <a href="https://schleuss.online/tags/retrocomputing" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>retrocomputing</span></a> <a href="https://schleuss.online/tags/githubactions" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>githubactions</span></a> <a href="https://schleuss.online/tags/tinytapeout" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>tinytapeout</span></a> <a href="https://schleuss.online/tags/synthesis" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>synthesis</span></a> <a href="https://schleuss.online/tags/testbench" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>testbench</span></a> <a href="https://schleuss.online/tags/hardware" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>hardware</span></a> <a href="https://schleuss.online/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://schleuss.online/tags/audio" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>audio</span></a> <a href="https://schleuss.online/tags/asic" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>asic</span></a> <a href="https://schleuss.online/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://schleuss.online/tags/dac" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>dac</span></a> <a href="https://schleuss.online/tags/pwm" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>pwm</span></a></p>
Mecrisp<p>The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are <a href="https://chaos.social/tags/Assembler" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Assembler</span></a>, <a href="https://chaos.social/tags/Forth" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Forth</span></a> and <a href="https://chaos.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a> on <a href="https://chaos.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a>. I am the author of <a href="https://chaos.social/tags/Mecrisp" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Mecrisp</span></a>, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with <span class="h-card" translate="no"><a href="https://fosstodon.org/@BrunoLevy01" class="u-url mention" rel="nofollow noopener" target="_blank">@<span>BrunoLevy01</span></a></span> (<a href="https://chaos.social/tags/FemtoRV" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FemtoRV</span></a> Gracilis) and I love <a href="https://chaos.social/tags/sizecoding" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>sizecoding</span></a> challenges (Byte-Athlon Champion in <a href="https://chaos.social/tags/Lovebyte" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Lovebyte</span></a> 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.</p>
Flux<p>I was getting the weirdest <a href="https://mastodon.social/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> test results until I spotted my test data didn't mean what I thought it meant... (DATAW=10) 🫢 <a href="https://mastodon.social/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a></p>
PipelineC<p><span class="h-card" translate="no"><a href="https://mastodon.online/@sylefeb" class="u-url mention" rel="nofollow noopener" target="_blank">@<span>sylefeb</span></a></span> for anyone wanting to follow along with the excellent <a href="https://fosstodon.org/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://fosstodon.org/tags/hardware" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>hardware</span></a> <a href="https://fosstodon.org/tags/hdl" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>hdl</span></a> <a href="https://fosstodon.org/tags/graphics" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>graphics</span></a> <a href="https://fosstodon.org/tags/eda" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>eda</span></a> <a href="https://fosstodon.org/tags/asic" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>asic</span></a> better than <a href="https://fosstodon.org/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://fosstodon.org/tags/vhdl" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>vhdl</span></a> but not <a href="https://fosstodon.org/tags/HLS" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>HLS</span></a> stuff going on 🤓 <br><a href="https://www.youtube.com/watch?v=XycwTFPDZ6w" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://www.</span><span class="ellipsis">youtube.com/watch?v=XycwTFPDZ6</span><span class="invisible">w</span></a></p>
IT News<p>What’s the Difference Between Tang 9K and 20K (It isn’t 11…) - [Grug Huhler] has been working with the Tang Nano 9K FPGA board. They are inexpens... - <a href="https://hackaday.com/2024/06/06/whats-the-difference-between-tang-9k-and-20k-it-isnt-11/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">hackaday.com/2024/06/06/whats-</span><span class="invisible">the-difference-between-tang-9k-and-20k-it-isnt-11/</span></a> <a href="https://schleuss.online/tags/tangnano" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>tangnano</span></a> <a href="https://schleuss.online/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://schleuss.online/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a></p>
IT News<p>The 6809 Lives On in an FPGA - At one point, the Motorola 6809 seemed like a great CPU. At the time it was a mode... - <a href="https://hackaday.com/2024/05/28/the-6809-lives-on-in-an-fpga/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">hackaday.com/2024/05/28/the-68</span><span class="invisible">09-lives-on-in-an-fpga/</span></a> <a href="https://schleuss.online/tags/retrocomputing" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>retrocomputing</span></a> <a href="https://schleuss.online/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://schleuss.online/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a></p>
Flux<p>One example, my division module handles signed fixed-point division with Gaussian rounding in ~100 lines of <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a>. There's a cocotb test bench and an accompanying blog post that explains how it works. <a href="https://mastodon.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a></p><p><a href="https://github.com/projf/projf-explore/tree/main/lib/maths" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">github.com/projf/projf-explore</span><span class="invisible">/tree/main/lib/maths</span></a></p>
IT News<p>Manta: An Open On-FPGA Debug Interface - We always can use more tools for FPGA debugging, and the Manta project by [Fischer... - <a href="https://hackaday.com/2024/05/01/manta-an-open-on-fpga-debug-interface/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">hackaday.com/2024/05/01/manta-</span><span class="invisible">an-open-on-fpga-debug-interface/</span></a> <a href="https://schleuss.online/tags/debuginterface" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>debuginterface</span></a> <a href="https://schleuss.online/tags/logicanalyser" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>logicanalyser</span></a> <a href="https://schleuss.online/tags/logicanalyzer" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>logicanalyzer</span></a> <a href="https://schleuss.online/tags/toolhacks" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>toolhacks</span></a> <a href="https://schleuss.online/tags/amaranth" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>amaranth</span></a> <a href="https://schleuss.online/tags/ethernet" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ethernet</span></a> <a href="https://schleuss.online/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://schleuss.online/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://schleuss.online/tags/uart" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>uart</span></a></p>
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