FCLC<p>Channeling my inner <span class="h-card" translate="no"><a href="https://hachyderm.io/@shafik" class="u-url mention" rel="nofollow noopener" target="_blank">@<span>shafik</span></a></span>, assuming a standard, compliant <a href="https://mast.hpc.social/tags/riscv" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>riscv</span></a> processor, what kind of float instructions can be executed on the vector unit of a processor that advertises </p><p>"RV32IMFDZve64f"</p><p><a href="https://mast.hpc.social/tags/HPC" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>HPC</span></a> <a href="https://mast.hpc.social/tags/IEEE754" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>IEEE754</span></a> <a href="https://mast.hpc.social/tags/SIMD" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>SIMD</span></a> <a href="https://mast.hpc.social/tags/RISCV" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>RISCV</span></a> <a href="https://mast.hpc.social/tags/RVV" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>RVV</span></a> </p><p><a href="https://github.com/riscvarchive/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">github.com/riscvarchive/riscv-</span><span class="invisible">v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf</span></a></p>